1. Field of the Invention
The invention relates a pixel structure and a method of fabricating the pixel structure.
2. Description of the Prior Art
A liquid crystal display (LCD) has gradually replaced a conventional cathode ray tube (CRT) display due to its small size, low radiation, and low power consumption. Generally speaking, an LCD panel includes an array substrate having thin film transistors thereon, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. The array substrate includes a plurality of pixel regions defined by a plurality of scan lines arranged in parallel, and a plurality of data lines arranged in parallel and perpendicular to the scan lines. Each pixel region is controlled by a thin film transistor as switch element and a pixel electrode to drive liquid crystal molecules to rotate in different extents for adjusting brightness outputs. The color filter disposed on the color filter substrate includes a plurality of red color filters, green color filters, and blue color filters corresponding to each pixel region so that the LCD panel can output high quality images with different colors.
Referring to FIGS. 1-6, FIGS. 1-6 illustrate a method for fabricating a pixel structure according to the prior art. As shown in FIG. 1, a substrate 12 having at least a transistor region 14 and a capacitor region 16 is provided. A patterned polysilicon layer 18 is then formed on the transistor region 14 and the capacitor region 16 of the substrate 12, in which the pattern polysilicon layer 18 disposed in the transistor region 14 is used for forming a source/drain region of the transistor and the patterned polysilicon layer 18 disposed in the capacitor region 16 is used for forming a bottom electrode of a capacitor. The process for forming the patterned polysilicon layer 18 can be accomplished with a standard process for fabricating low temperature polysilicon layers. For instance, an amorphous silicon layer (not shown) can be formed on the surface of the substrate 12, and an excimer laser annealing process is conducted to transform the amorphous silicon layer into a polysilicon layer. Next, a patterning process is performed to remove a portion of the polysilicon layer and form the patterned polysilicon layer 18 on the substrate 12.
Next, as shown in FIG. 2, a gate dielectric layer 20 composed of silicon oxide is formed on the substrate 12 to cover the patterned polysilicon layer 18. A patterned photoresist layer 22 is then formed on the gate dielectric layer 20 and an ion implantation is conducted by using the patterned photoresist layer 22 as mask to inject p-type or n-type dopants into the patterned polysilicon layer 18. The result forms a source/drain region 24 in the patterned polysilicon layer 18 of the transistor region 14.
As shown in FIG. 3, a conductive layer (not shown) composed of molybdenum is formed on the gate dielectric layer 20, and a patterning process is performed to remove a portion of the conductive layer for forming a gate 26 on the gate dielectric layer 20 of the transistor region and an upper capacitor electrode 28 on the gate dielectric layer 20 of the capacitor region 16. An ion implantation is then conducted by using the gate 26 as mask to inject p-type or n-type dopants into the patterned polysilicon layer 18. The result forms a lightly doped drain 30 in the patterned polysilicon layer 18 and completes the fabrication of a transistor in the transistor region 14 and a capacitor in the capacitor region 16.
Next, as shown in FIG. 4, a dielectric layer 32 is deposited on the gate dielectric layer 20, the gate 26, and the upper capacitor electrode 28, and a patterning process is performed to form a plurality of via holes 34 in the dielectric layer 32 and the gate dielectric layer 20.
As shown in FIG. 5, a patterned metal layer is formed on the dielectric layer and into each of the via holes 34, thereby forming a plurality of wires 36 connecting to the source/drain region 24.
As shown in FIG. 6, another dielectric layer 38 serving as a planarizing layer is formed on the wires 36, and a patterning process is performed by using a patterned photoresist layer (not shown) as a mask to conduct an etching process to form at least an opening 40 in the dielectric layer 38. Next, a patterned transparent conductive layer is formed on the dielectric layer 38 and into the opening 40 to form a corresponding pixel electrode 42. This completes the fabrication of a typical pixel structure.
It should be noted that the aforementioned process typically takes at least seven photomasks to complete the entire process for fabricating a pixel structure, which increases the overall cost of the fabrication significantly. Additionally, the capacitor fabricated along the transistor is typically composed of a polysilicon layer, a dielectric layer composed of silicon oxide, and a conductive layer composed of molybdenum. Despite the capacitor having such structure may qualify the demand for typical pixel structures, the capacity of these capacitors is still insufficient under many circumstances. Hence, finding a way to reduce the overall fabrication cost while increasing the capacity for the capacitor has become an important task.